1. Field of the Invention
This invention relates to a personal computer (PC) system and more particularly to a core section within the PC which can be asynchronously reset, either fully reset or partially reset.
2. Description of the Relevant Art
Personal information devices (herein referred to as PIDs) are well known in the industry. Typically, a PID includes any computer-based device which can store and manipulate data according to a user-defined program. Common types of PIDs are: notebook computers, subnotebook computers, digital assistants (test units, meters, etc.), electronic calendars, organizers, "smart" phones, etc. Depending upon their usage, PIDs are instrumental as a portable tool for communicating, computing and generally organizing day to day activities of a user.
PIDs typically employ both an AC power supply and/or battery pack (primary power source) as well as a backup power supply (secondary power source). The battery pack allows the PID operation remote from an AC plug in. Hence, the device enables a user to reference and manipulate information stored within the PID at a client's place of business, at the user's home, or while the user is traveling, for example.
At a minimum, a PID is implemented using a set of basic subsystems including: a central processing unit (CPU), an input/output structure, a memory, a control bus, a data bus and an address bus. Each of the above basic subsystems of the PID can be embodied upon separate silicon substrates or upon a single monolithic substrate, as an "integrated circuit". When one of the subsystems included upon the integrated circuit is the CPU, the integrated circuit is referred to as an "integrated processor". Depending upon the complexity of the PID, additional subsystems can be added to the basic subsystems listed above. Further, the basic subsystems as well as the additional subsystems can be configured upon the same silicon substrate as the integrated processor.
One of the basic subsystems included in a PID, as mentioned above, is a memory. The memory is typically composed of dynamic random access memory, or DRAM. DRAM has the requirement that each memory cell be refreshed. Refresh is a process wherein the contents of the memory cell are transferred out and subsequently transferred back into the memory cell. Refresh is required because capacitors associated with the cells cannot permanently retain voltage. The voltage represents the value stored in the cell, and thus the value can be lost over time. Because a given cell is not guaranteed to be accessed within a given amount of time by the natural operation of the system, refresh logic is included in either the memory controller that is typically coupled to the DRAM, included within the DRAM itself, or coupled to some combination of the memory controller and/or the DRAM. Two typical refresh schemes are CAS before RAS refresh and self refresh.
In CAS before RAS refresh, two interface signals between the DRAM and its controller are driven active in the opposite order of a normal access. During normal read or write accesses to a DRAM, RAS is driven active and then later CAS is driven active. RAS before CAS signaling causes the DRAM to transfer the contents of a requested memory location to its associated output. However, if CAS is driven active and then later RAS is driven active (i.e. CAS before RAS), the DRAM interprets the request as a refresh request. Subsequently, a refresh occurs in accordance with an incremented register within the DRAM. By periodically using the refresh signalling technique, a computer system can keep the entire DRAM refreshed and each memory cell will continue to maintain the value that was last stored into it by the memory controller.
In self refresh, the DRAM is signaled to begin refresh similar to the CAS before RAS refresh scheme, wherein CAS is driven active followed by RAS. However, using a self refresh scheme will allow the DRAM to continuously execute refresh cycles until CAS and RAS are driven inactive. Conversely, only one refresh cycle is preformed in DRAMS using CAS before RAS refresh for each CAS/RAS activation cycle.
The basic subsystems listed above are included in the IBM-compatible, AT-style personal computer (PC) architecture. The AT architecture is a well-known and popular configuration for various PIDs, and has enjoyed widespread acceptance in the computer industry as evidenced by its use in a large majority of the PCs currently being sold. In addition to the basic subsystems listed above, AT-style PCs employ expanded basic subsystems necessary for specific PID applications. In addition to other subsystems, an AT-style system used as a PID include the following expanded basic subsystems: a real time clock (RTC) unit and configuration static random access memory (configuration RAM).
The RTC unit serves to maintain time and date information within the PID. Typically, the RTC unit is adapted to receive an oscillator input for incrementing the RTC register value. The oscillator input is normally driven by an external oscillator crystal which is configured to oscillate at a defined frequency. The RTC register is then read by an operating system at boot time, and the read value is used to update the time and date values associated with the operating system running upon the integrated processor. The operating system then maintains the time and date during normal operation.
Configuration RAM maintains information regarding many of the subsystems (components) coupled within or to the integrated processor and forming the PID. Exemplary information maintained within the configuration RAM includes the number and size of fixed disk drives, the size of main memory coupled to the CPU, information about various peripheral components installed in the expansion slots, etc. The user or manufacturer of the PID defines the configuration of the components when the PID is first powered on, whereby application of power causes information storage into the configuration RAM. Whenever components are updated, added or removed from the PID, the configuration RAM is changed to reflect the new status of the PID components. Accordingly, the PID can always determine information about components currently installed by examining the information stored in the configuration RAM. Configuration RAM is well known in the industry and is commonly termed "CMOS RAM".
In order for the aforementioned RTC unit to maintain accurate time and date information, and the configuration RAM to maintain the current configuration information, these expanded basic subsystems must remain powered even when the remaining subsystems are powered off. Early PIDs employ a separate battery (secondary power source), typically a lithium cell, to supply power to the RTC unit and configuration RAM while the remaining subsystems are selectively powered by the primary source. In the above configuration, power is always drawn from the secondary power source regardless of the PID power state.
Various semiconductor manufacturers have produced integrated circuits that have integrated the RTC unit, the configuration RAM, and the battery cell into a single integrated circuit. It would be advantageous in a PID to include the RTC unit and the configuration RAM with other subsystems on a single integrated circuit. Such integration provides enhanced minimization and reduces the number of separate (discrete) subsystems required to build a PID. Reducing the number of discrete subsystems and placing as many subsystems as possible on a single monolithic substrate lowers the cost of the PID. However, an integrated circuit of this type would require an apparatus which can reset the basic subsystems and additional subsystems to a known state without disturbing the contents of the expanded basic subsystems such as the RTC unit and configuration RAM. Furthermore, an integrated circuit which includes such subsystems requires selective power capability (i.e. an apparatus which can apply power to the RTC unit and configuration RAM during times when the remaining integrated subsystems are powered off). If such an apparatus is not provided, the contents of the configuration RAM and the real time clock sections would be lost each time the PID is powered down or reset.
In addition to needing selective power capabilities, PIDs must also provide high performance while utilizing low power. The low power requirement exists because the PID is configured to operate from a battery pack. Subsystems which operate at lower power will therefore function for a longer period of time than higher power subsystems. Several power management techniques have been implemented by PID manufacturers to accomplish low power designs.
One such power management technique is to lower the voltage provided to the integrated circuits that comprise subsystems of a PID. However, the lowest voltage that can be used is limited by a number of factors, including noise margin and the semiconductor technology that was used to manufacture the integrated circuits. Noise margin refers to the resilience of a circuit to the presence of random fluctuations in the electrical signals which are used to communicate within the circuit.
Another power management technique typically used within an integrated circuit is to temporarily disable the clock signal to circuits that are idle for a period of time. With the clock signal stopped, the inputs to the circuit will be held constant and thus no switching of the circuits will occur. In many semiconductor technologies, such as CMOS, very little power is used if no switching occurs.
Another power management technique is to remove the power input from peripheral devices when those devices are idle for a period of time. The term "peripheral component" or "peripheral device" refers to an electronic component which is coupled to a peripheral controller linked to a peripheral bus. The peripheral controller is defined as an additional subsystem. Peripheral devices and associated peripheral controllers are not critical to PID functionality, but nonetheless expand functionality of the PID when included. Exemplary peripheral devices are fixed disk drives, PCMCIA devices, etc. Due to the nature of subsystems integrated as an integrated circuit, powering off of peripheral components requires a buffer inserted between the peripheral component and the integrated circuits which interface to the peripheral component when the peripheral component is to be powered off while connected to other components which remain powered on.
Integrated circuits are typically divided into a core section and one or more input/output driver sections. The core section includes circuits necessary to provide the basic, expanded, and additional subsystem functions of the integrated circuit. Each input/output driver section provides the interface between the core and a corresponding peripheral device. Thus, the input/output driver section is coupled between the core and pins on the exterior of the package containing the integrated circuit.
One or more input/output driver circuits included in an input/output driver section typically contain a transistor for driving a pin associated with an input/output driver section to a voltage representing a logical one. Another transistor is included for driving the pin to a voltage representing a logical zero. In some driver circuits, the inputs to the logical one and logical zero-driving transistors are configured to be off simultaneously at certain times. Such a configuration is known as a "tri-state" driver. The term "tri-state" means that the associated input/output pin may take on three values: logical one, logical zero, and unknown (or floating). The floating or unknown value may correspond to any voltage.
If a peripheral component attached to an input/output pin of an integrated circuit having input/output drivers as described above is to be powered off, then it is necessary to prevent the integrated circuit from driving current (via an output signal through an input/output pin) into the powered down device. Such current could damage the integrated circuit or the receiving peripheral component. The external buffer is used to prevent this damage. The input/output pins of the integrated circuit are coupled to one side of the buffer, and the pins of the peripheral component are coupled to the opposite side of the buffer. A control input to the buffer is provided. When the control input is in the connect state, the respective input/output pins of the two devices are coupled together. However, when the control input is in the disconnect state, the respective input/output pins of the two devices are not coupled together. Thus, when a peripheral component is powered down, the control inputs of the buffers associated with that component are driven to the disconnect state and the integrated circuit is electrically isolated from the peripheral component.
Unfortunately, the buffers that are required to enable peripheral component power off are costly. Also, controlling the buffer requires extra signals to be added to the PID, also possibly adding cost. A solution for powering down peripheral components without requiring external buffers in a PID is needed.